Semiconductor device

ABSTRACT

A semiconductor device capable of deleting data already recorded on a recording medium when information indicative of prohibition of copying is detected from picture signal. Input portion receives an input picture signal, and copy protection information detecting portion detects copy protection information included in the picture signal input from the input portion. Compressing portion compresses the picture signal, and compressed data output portion outputs compressed data obtained by the compressing portion. Specification information output portion generates and outputs specification information specifying a position of the compressed data where the information indicative of prohibition of copying was detected first by the copy protection information detecting portion. A device for recording the compressed data can specify the head of unnecessary compressed information by looking up the specification information, whereby the unnecessary information can be deleted from the recording medium.

BACKGROUND OF THE INVENTION

[0001] (1) Field of the Invention

[0002] The present invention relates to a semiconductor device, and more particularly, to a semiconductor device for compressing picture signal.

[0003] (2) Description of the Related Art

[0004] In recent years, an increasing number of video recorders which record and reproduce audio and video signals with the use of a DVD (Digital Versatile Disk) or HDD (Hard Disk Drive) are put on the market.

[0005] Generally, as an information compression scheme used in recording signals on such recording media, MPEG (Moving Picture Coding Experts Group)-2 Video format is used for video signal, and MPEG1 Layer 1 or 2 or the like is used for audio signal.

[0006] To store the signals compressed by such methods on a recording medium, both of AV (Audio and Video) signals, including synchronizing signal, need to be further combined into one and then be multiplexed into data in a format suited for the physical format, protocol, etc. peculiar to DVD or HDD. As such format, MPEG2 PS (Program Stream) or TS (Transport Stream) is generally used.

[0007] Recently, one-chip LSIs (Large Scale Integrated Circuits) capable of compressing and multiplexing AV signals have come onto the market. In the present specification, this type of LSI is called MPEG2 encoder.

[0008] Meanwhile, with the commercialization of video recorders using DVD or HDD as a recording medium, a need has arisen to protect contents against illegal copying etc., and a technique of inserting a copy protection signal in video signals is used as one of measures to meet the need.

[0009] Specifically, a signal indicating “copy permitted”, “one copy permitted” or “copy not permitted” is inserted in a VBI (Vertical Blanking Interval) of every field of video signal, and a video recorder looks up such signals to restrict copying.

[0010]FIG. 12 illustrates an exemplary configuration of a conventional video decoder using an HDD as a recording medium.

[0011] In the figure, an NTSC (National TV Standards Committee) decoder 10 converts a video signal into a digital signal and outputs the converted signal.

[0012] A VBI detecting section 11 detects protection information inserted in the VBI of the NTSC signal and notifies a CPU 19 of the information via a bus 22.

[0013] An audio A/D (Analog to Digital) converter 12 converts an audio signal into a digital signal.

[0014] An MPEG2 encoder 13 compresses the digitized NTSC signal (hereinafter called video data) and the digitized audio signal (hereinafter called audio data) according to MPEG2 format, and outputs the result.

[0015] An IDE (Integrated Drive Electronics) I/F (Interface) 14 controls an HDD 15.

[0016] Under the control of the IDE I/F 14, the HDD 15 records the data supplied from the MPEG2 encoder 13 into a predetermined region thereof, and also reads out the data recorded in the predetermined region to be supplied to an MPEG2 decoder 16.

[0017] The MPEG2 decoder 16 decodes the data compressed according to MPEG2 format, and outputs the video data and the audio data.

[0018] A video AMP 17 converts the video data to analog NTSC video signal, and outputs the converted signal.

[0019] An audio D/A (Digital to Analog) converter 18 converts the audio data to analog signal and outputs the result.

[0020] The CPU (Central Processing Unit) 19 controls the individual parts of the device and performs various operations in accordance with programs stored in a flash ROM (Read Only Memory) 20.

[0021] The flash ROM 20 stores programs to be executed by the CPU 19 and various other data.

[0022] An SDRAM (Synchronous Dynamic Random Access Memory) 21 temporarily stores programs being executed by the CPU 19 as well as data derived in the middle of operations.

[0023] The bus 22 interconnects the VBI detecting section 11, MPEG2 encoder 13, IDE I/F 14, MPEG2 decoder 16, CPU 19, flash ROM 20 and SDRAM 21, and permits exchange of data between these elements.

[0024] Operation of the conventional device will be now described.

[0025] Video and audio signals are input to the NTSC decoder 10 and the audio A/D converter 12, respectively, whereupon the NTSC decoder 10 converts the video signal to digital signal in compliance with an encode request from the CPU 19 and outputs the converted signal, and the audio A/D converter 12 converts the audio signal to digital signal and outputs the result.

[0026] The VBI detecting section 11 detects the protection information inserted in the VBI included in each field of the video data output from the NTSC decoder 10, and supplies the detected information to the CPU 19 via the bus 22. The protection information indicates, for example, “copy permitted” or “one copy permitted” or “copy not permitted”, and based on the information the CPU 19 determines whether copying is permitted or not.

[0027] On detecting “copy permitted”, the CPU 19 instructs the MPEG2 encoder 13 to start encoding. As a result, the MPEG2 encoder 13 compresses the video data supplied from the NTSC decoder 10 and the audio data output from the audio A/D converter 12, according to the MPEG2 scheme, and outputs the obtained data.

[0028] The CPU 19 instructs the IDE I/F 14 to store the data output from the MPEG2 encoder 13 in a predetermined region of the HDD 15. Operation like this is continued until the input of video and audio signals ends.

[0029] Reproduction of data stored in the HDD 15 will be now described.

[0030] The CPU 19 instructs the IDE I/F 14 to reproduce certain data, whereupon the IDE I/F 14 reads out corresponding data stored in a predetermined region of the HDD 15 and supplies the data to the MPEG2 decoder 16 via the bus 22.

[0031] The MPEG2 decoder 16 decodes the data supplied from the IDE I/F 14, and supplies the obtained video and audio data to the video AMP 17 and the audio D/A converter 18, respectively.

[0032] The video AMP 17 converts the video data supplied from the MPEG2 decoder 16 into analog signal and outputs the result. The audio D/A converter 18 converts the audio data supplied from the MPEG2 decoder 16 into analog signal and outputs the result.

[0033] When the information inserted in the VBI is reproduced, the obtained information sometimes includes noise superimposed thereon, and in such cases, the copy protection signal can be erroneously detected.

[0034] To prevent such erroneous detection, when an identical signal is detected consecutively a predetermined number of times (e.g., ten times), for example, the detected signal may be judged valid and the specified operation may be executed, whereby the probability of erroneous operation can be lessened.

[0035] However, to carry out such control, while the protection information is detected consecutively the predetermined number of times, the MPEG2 encoder 13 needs to be operated to store the generated data in the HDD 15, and when an identical protection signal is detected the predetermined number of times and thus a requested operation is established, the requested operation is executed. Accordingly, even in the case where the requested operation signifies “copy not permitted”, data is stored in the HDD 15.

[0036] To solve the problem, data that has been stored in the HDD 15 may be deleted afterward. However, once data is compressed by the MPEG2 encoder 13, the correspondence of the compressed data to video data before the compression is not clear. Thus, since it is not clear from which location to which location of data in the HDD 15 should be deleted, it is difficult to delete the compressed data afterward.

SUMMARY OF THE INVENTION

[0037] The present invention was created in view of the above circumstances, and an object thereof is to provide a semiconductor device which is robust against noise and which also permits compressed recorded data to be deleted afterward.

[0038] To achieve the above object, there is provided a semiconductor device for compressing picture signal. The semiconductor device comprises input portion for receiving an input picture signal, copy protection information detecting portion for detecting copy protection information included in the picture signal input from the input portion, compressing portion for compressing the picture signal, and compressed data output portion for outputting compressed data obtained by the compressing portion.

[0039] The above and other objects, features and advantages of the present invention will become apparent from the following description when taken in conjunction with the accompanying drawings which illustrate preferred embodiments of the present invention by way of example.

BRIEF DESCRIPTION OF THE DRAWINGS

[0040]FIG. 1 is a diagram illustrating the principle of operation according to the present invention;

[0041]FIG. 2 is a diagram showing an exemplary configuration according to an embodiment of the present invention;

[0042]FIG. 3 is a diagram showing in detail an exemplary configuration of an MPEG2 encoder appearing in FIG. 2;

[0043]FIG. 4 is a diagram illustrating details of a VBI;

[0044]FIG. 5 is a diagram also illustrating details of the VBI;

[0045]FIG. 6 is a chart illustrating an example of copy protection information inserted in the VBI;

[0046]FIG. 7 is a chart illustrating an example of notification data;

[0047]FIG. 8 is a chart illustrating an example of specification information;

[0048]FIG. 9 is a flowchart illustrating an example of process executed by a CPU;

[0049]FIG. 10 is a flowchart illustrating an example of process executed by the MPEG2 encoder;

[0050]FIG. 11 is a chart showing examples of commands exchanged between the CPU and the MPEG2 encoder; and

[0051]FIG. 12 is a diagram showing an exemplary configuration of a conventional video decoder using an HDD as a recording medium.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0052] Embodiments of the present invention will be hereinafter described with reference to the drawings.

[0053]FIG. 1 illustrates the principle of operation according to the present invention. As shown in the figure, a semiconductor device 1 according to the present invention comprises input portion 2, copy protection information detecting portion 3, compressing portion 4, compressed data output portion 5, and specification information output portion 6.

[0054] The input portion 2 receives a picture signal input from outside.

[0055] The copy protection information detecting portion 3 detects copy protection information included in the picture signal input from the input portion 2.

[0056] The compressing portion 4 compresses the picture signal.

[0057] The compressed data output portion 5 outputs the compressed data obtained by the compressing portion 4.

[0058] When copy protection information is detected by the copy protection information detecting portion 3, the specification information output portion 6 outputs specification information specifying a corresponding part of the compressed data.

[0059] Operation in accordance with the illustrated principle will be now described.

[0060] When the semiconductor device 1 is supplied with a picture signal from outside, the input portion 2 receives the input picture signal and supplies the signal to the copy protection information detecting portion 3.

[0061] The copy protection information detecting portion 3 detects the copy protection information inserted in the input picture signal and supplies the detected information to the specification information output portion 6; it also supplies the picture signal to the compressing portion 4.

[0062] The compressing portion 4 subjects the picture signal supplied thereto to an image compression process according to the MPEG2 scheme, for example, and supplies the result to the compressed data output portion 5.

[0063] The compressed data output portion 5 outputs picture data obtained through the compression by the compressing portion 4.

[0064] If identical copy protection information (e.g., information indicative of prohibition of copying) is consecutively detected a predetermined number of times (e.g., ten times) by the copy protection information detecting portion 3, the specification information output portion 6 outputs specification information specifying a corresponding part of the compressed data output from the compressing portion 4. The specification information to be used may, for example, be the number of bytes as counted from the head of the compressed data with respect to which the copy protection information was detected first (first time).

[0065] Thus, the copy protection information is detected within the semiconductor device 1, whereby copy protection can be prevented from being broken through easily by modifying the output signal from the copy protection information detecting portion 3.

[0066] Also, when identical copy protection information has been detected the predetermined number of times by the copy protection information detecting portion 3, the specification information output portion 6 outputs specification information specifying the corresponding part of the compressed data. Accordingly, where the compressed data output from the semiconductor device 1 is recorded on a recording medium, for example, it is possible to specify and delete an unnecessary part from among the data already recorded.

[0067] Namely, the part with respect to which the copy protection information was detected first can be specified by the specification information, thus making it possible to specify and delete a part of data which is prohibited from being copied and which is already recorded on the recording medium, for example.

[0068] An embodiment of the present invention will be now described.

[0069]FIG. 2 shows an exemplary configuration according to the embodiment of the present invention. As shown in the figure, a recorder including a semiconductor device (MPEG2 encoder 40) according to the present invention comprises an NTSC decoder 10, an audio A/D converter 12, an IDE I/F 14, an HDD 15, an MPEG2 decoder 16, a video AMP 17, an audio D/A converter 18, a CPU 19, a flash ROM 20, an SDRAM 21, a bus 22, and an MPEG2 encoder 40. In this embodiment, as compared with FIG. 12, the VBI detecting section 11 is omitted and the MPEG2 encoder 13 is replaced by the MPEG2 encoder 40.

[0070] The NTSC decoder 10 converts an NTSC standard-based video signal into digital signal complying with the ITU-R656 standard, and outputs the converted signal.

[0071] The audio A/D converter 12 converts an input audio signal into a digital signal of I2S format.

[0072] The MPEG2 encoder 40 encodes the video data supplied from the NTSC decoder 10 into MPEG2 Video MP@ML format, and also encodes the audio data supplied from the audio A/D converter 12 into MPEG1 Audio Layer 2 format. Further, these two types of encoded data are subjected to system multiplexing into MPEG2 PS format, and the resulting data is output as an 8-bit parallel data stream.

[0073] The IDE I/F 14, which is an interface for the HDD 15, controls the HDD 15 to write and read data into and from a predetermined region thereof.

[0074] The HDD 15 operates under the control of the IDE I/F 14, to record the data supplied from the MPEG2 encoder 40 in a predetermined region thereof and also to read out the data recorded in the predetermined region to be supplied to the MPEG2 decoder 16.

[0075] The MPEG2 decoder 16 decodes a data stream that was compressed in the MPEG2 format, and converts the resulting data into video data of ITU-R656 format and audio data of I2S format, which are then output.

[0076] The video AMP 17 converts the video data of ITU-R656 format into an analog signal of NTSC format, and outputs the converted signal.

[0077] The audio D/A converter 18 converts the audio data of I2S format into analog signal and outputs the result.

[0078] The CPU 19 controls the individual parts of the recorder and also performs various operations in accordance with programs stored in the flash ROM 20.

[0079] The flash ROM 20 stores programs to be executed by the CPU 19 and various other data.

[0080] The SDRAM 21 temporarily stores programs being executed by the CPU 19 as well as data derived in the middle of operations.

[0081] The bus 22 interconnects the IDE I/F 14, MPEG2 decoder 16, CPU 19, flash ROM 20, SDRAM 21 and MPEG2 encoder 40 to permit exchange of data between these elements.

[0082]FIG. 3 shows in detail an exemplary configuration of the MPEG2 encoder 40 appearing in FIG. 2. As shown in the figure, the MPEG2 encoder 40 comprises a video control section 41, a video encoder 42, an audio encoder 43, a multiplexing section 44, an I/F 45, a CPU 46, a DMAC (Direct Memory Access Controller) 47, and a bus 48.

[0083] The video control section 41 stores the video data supplied from the NTSC decoder 10 temporarily in the SDRAM 21, then successively acquires the stored video data in accordance with the progress of a compression process performed by the video encoder 42, and supplies the acquired data to the video encoder 42.

[0084] The video encoder 42 encodes the video data supplied from the video control section 41 to convert same into data of MPEG2 Video MP@ML format, and outputs the converted data.

[0085] The audio encoder 43 encodes the audio data supplied from the audio A/D converter 12 to convert same into data of MPEG1 Audio Layer 2 format, and outputs the converted data.

[0086] The multiplexing section 44 multiplexes the video data supplied from the video encoder 42 and the audio data supplied from the audio encoder 43, to generate a data stream of MPEG2 PS format, which is then output via the bus 22.

[0087] The I/F 45 is an interface which mainly takes care of exchanging data with the SDRAM 21.

[0088] The CPU 46 controls the individual parts of the MPEG2 encoder 40 in accordance with firmware stored in the SDRAM 21.

[0089] The DMAC 47 exchanges data directly with the SDRAM 21 etc. without through the agency of the CPU 46.

[0090] Operation of the embodiment of the present invention will be now described.

[0091] When power supply to the recorder is started, first, the CPU 19 acquires the firmware for the MPEG2 encoder 40 stored in the flash ROM 20, and stores the firmware in a predetermined region of the SDRAM 21.

[0092] The CPU 46 of the MPEG2 encoder 40 operates in accordance with the firmware thus stored in the SDRAM 21.

[0093] Picture recording operation will be now described.

[0094] After completion of the initialization described above, video and audio signals are supplied to the NTSC decoder 10 and the audio A/D converter 12, respectively, whereupon the NTSC decoder 10 converts the video signal into video data of ITU-R656 format and outputs the converted data, while the audio A/D converter 12 converts the audio signal into audio data of I2S format and outputs the converted data.

[0095] In accordance with instructions from the CPU 19, the video control section 41 of the MPEG2 encoder 40 successively stores the input video data in the SDRAM 21 via the I/F 45.

[0096] The CPU 46 acquires the video data stored in the SDRAM 21 and detects copy protection information inserted in the VBI of the video data.

[0097] The VBI corresponds to a region of lines 10 to 20 of the top field, as shown in FIG. 4, and to a region from the latter half of line 272 to the former half of line 283 of the bottom field, as shown in FIG. 5. These regions, except for the interval used for synchronization, permit the insertion of information such as teletext.

[0098]FIG. 6 illustrates an example of copy protection information. As shown in the figure, the copy protection information is represented by bit A and bit B. If bits A and B are both “0”, this combination indicates “copy permitted”. If bit A is “0” and bit B is “1”, the combination indicates “undefined”, and if bit A is “1” and bit B is “0”, the combination indicates “one copy permitted”. If bits A and B are both “1”, the combination indicates “copy not permitted”.

[0099] The CPU 46 writes the detected copy protection information or information relating thereto into a predetermined region of the SDRAM 21, and generates an interrupt to notify the CPU 19 of the information. A process relating to the copy protection information will be described later.

[0100] The video data with respect to which the copy protection information has been detected by the CPU 46 is supplied to the video encoder 42 via the video control section 41.

[0101] The video encoder 42 encodes the video data to convert same into data of MPEG2 Video MP@ML format, and outputs the converted data.

[0102] The audio encoder 43 encodes the audio data supplied from the audio A/D converter 12 to convert same into data of MPEG1 Audio Layer 2 format, and outputs the converted data.

[0103] The multiplexing section 44 multiplexes the video data supplied from the video encoder 42 and the audio data supplied from the audio encoder 43 to generate a data stream of MPEG2 PS format, and outputs the data stream via the bus 22.

[0104] The data stream output from the MPEG2 encoder 40 in this manner is written into a predetermined region of the HDD 15 via the IDE I/F 14.

[0105] The process relating to the copy protection information will be now described.

[0106] As mentioned above, on detecting the copy protection information, the CPU 46 stores the information in a predetermined region of the SDRAM 21 and also generates an interrupt with respect to the CPU 19 to notify the CPU 19 of the detected protection information.

[0107]FIG. 7 illustrates an example of information (hereinafter referred to as notification data) written into the SDRAM 21. As shown in the figure, the notification data is constituted by three pieces of information, that is, copy restriction signal information notification command, state notification code, and state of copy protection signal, each consisting of 8 bits.

[0108] The copy restriction signal information notification command is a command indicating notification of copy restriction signal information, and is represented by “0x02”.

[0109] The state notification code is a code indicating notification of state and is represented by “0x00”.

[0110] The state of copy protection signal corresponds to bits A and B shown in FIG. 6: “0x00” indicates “copy permitted” and “0x02” indicates “one copy permitted”.

[0111] When “0x03” corresponding to “copy not permitted” is detected from the VBI, for example, the CPU 46 writes “0x1000003” into a predetermined region of the SDRAM 21 and generates an interrupt with respect to the CPU 19.

[0112] As a consequence, the CPU 19 reads out “0x1000003” from the predetermined region of the SDRAM 21, analyzes this notification data, and recognizes that “copy not permitted” has been detected.

[0113] Similarly, when “copy not permitted” is again detected from the VBI, the CPU 46 writes “01x000003” into the SDRAM 21 and generates an interrupt, as in the aforementioned case.

[0114] The CPU 19 reads out and analyzes the notification data written in the SDRAM 21, and increments the count of a counter if the notified state is the same as the previous one. In the above example, “copy not permitted” has been detected again, and accordingly, the CPU 19 increments the count of the counter.

[0115] The aforementioned operation is repeated, and if the count of the counter reaches “10”, the CPU 19 requests the MPEG2 encoder 40 to stop the encoding process, and also requests same to supply specification information specifying a time point at which “copy not permitted” was detected for the first time.

[0116] As a consequence, the video control section 41 of the MPEG2 encoder 40 stops supplying the video data to the video encoder 42, stores specification information specifying the time point at which “copy not permitted” was detected first, into a predetermined region of the SDRAM 21, and generates an interrupt.

[0117]FIG. 8 illustrates an example of specification information stored in the SDRAM 21 at this time. In the illustrated example, the specification information is constituted by copy restriction signal information notification command, position information notification code, byte length of target position information value, and target position information.

[0118] The copy restriction signal information notification command is represented by “0x10” and indicates that the information concerned is the copy restriction signal information.

[0119] The position information notification code is represented by “0x01” and indicates that the information concerned notifies position information.

[0120] The byte length of target position information value represents the byte length of expression of target position information indicating a position where target copy protection information exists.

[0121] The target position information indicates the number of bytes as counted from the head of the stream where the head of a PS packet including the head of a field with respect to which “copy not permitted” was detected first, or the head of the target field, exists.

[0122] The target position information may be information indicating the number of bytes as counted from the stream head where the tail position of a field immediately preceding that with respect to which “copy not permitted” was detected first, or the tail position of a PS packet including the tail position of the immediately preceding field, exists.

[0123] Also, the target position information may be generated using GOP (Group of Pictures), to indicate the number of bytes as counted from the stream head where the head position of a GOP including the field with respect to which “copy not permitted” was detected first, or the head position of a PS packet including the head position of the GOP, exists.

[0124] Further, the target position information may be information indicating the number of bytes as counted from the stream head where the tail position of a field immediately preceding that with respect to which “copy not permitted” was detected first, or the tail position of a GOP including the tail position of the immediately preceding field, exists.

[0125] For example, in the case where the target position is at 100 Mbytes from the stream head, 100 M=0x5F5E100 and the number of bytes of the target position information value=0x04; accordingly, “0x10010405F5E100” is written into the SDRAM 21.

[0126] The CPU 19 detects the generation of the interrupt and thus reads out the specification information from the SDRAM 21. The CPU 19 then extracts the target position information, and supplies the extracted information to the IDE I/F 14 to request same to delete the corresponding part.

[0127] As mentioned above, the target position information indicates the number of bytes as counted from the stream head where the head of the PS packet including the field with respect to which “copy not permitted” was detected for the first time exists, and accordingly, the IDE I/F 14 deletes the unnecessary part (from the position where “copy not permitted” is detected first to the end) of the data already written into the HDD 15.

[0128] Consequently, among the data recorded in the HDD 15, a part which is prohibited from being copied can be deleted afterward.

[0129] Processes performed in the above embodiment will be now described with reference to FIGS. 9 through 11.

[0130]FIG. 9 is a flowchart illustrating an example of process executed by the CPU 19. Upon start of the process shown in the flowchart, the following steps are executed.

[0131] Step S30:

[0132] The CPU 19 resets the counter which counts the number of times “copy not permitted” is detected.

[0133] Step S31:

[0134] The CPU 19 supplies an encode start command to the MPEG2 encoder 40 to cause same to start encoding.

[0135] Step S32:

[0136] The CPU 19 determines whether or not an interrupt has been generated by the MPEG2 encoder 40. If an interrupt has been generated, the flow proceeds to Step S33; if not, Step S32 is repeated.

[0137] Step S33:

[0138] The CPU 19 reads out the notification data stored in the SDRAM 21 and determines whether or not “copy not permitted” has been detected. If “copy not permitted” has been detected, the flow proceeds to Step S35; otherwise the flow proceeds to Step S34.

[0139] Step S34:

[0140] The CPU 19 resets the counter, whereupon the flow returns to Step S32 to repeat same.

[0141] Step S35:

[0142] The CPU 19 increments the counter by “1”.

[0143] Step S36:

[0144] The CPU 19 determines whether or not the value of the counter has reached a predetermined value (e.g., “10”). If the predetermined value is reached, the flow proceeds to Step S37; if not, the flow returns to Step S32 to repeat same.

[0145] Step S37:

[0146] The CPU 19 supplies an encode stop command to the MPEG2 encoder 40 to cause same to stop encoding.

[0147] Step S38:

[0148] The CPU 19 reads out the specification information written into the SDRAM 21 by the MPEG2 encoder 40.

[0149] Step S39:

[0150] The CPU 19 extracts the target position information from the specification information to specify the position of data to be deleted, and notifies the IDE I/F 14 of the specified position.

[0151] Step S40:

[0152] The CPU 19 instructs the IDE I/F 14 to delete the specified data.

[0153] Referring now to FIG. 10, a process executed by the CPU 46 of the MPEG2 encoder 40 will be described. Upon start of the process shown in the flowchart, the following steps are executed.

[0154] Step S50:

[0155] The CPU 46 determines whether or not an encode start command to start encoding has been received from the CPU 19. If an encode start command has been received, the flow proceeds to Step S51; if not, Step S50 is repeated.

[0156] Step S51:

[0157] The CPU 46 sends a control signal to the video control section 41 to cause same to start an encoding process.

[0158] Step S52:

[0159] The CPU 46 detects the copy protection information inserted in the VBI of the video data read from the SDRAM 21.

[0160] Step S53:

[0161] The CPU 46 writes notification data, such as one shown in FIG. 7, into a predetermined region of the SDRAM 21.

[0162] Step S54:

[0163] The CPU 46 generates an interrupt with respect to the CPU 19.

[0164] Step S55:

[0165] The CPU 46 determines whether or not an encode stop command to stop encoding has been received from the CPU 19. If an encode stop command has been received, the flow proceeds to Step S56; if not, the flow returns to Step S52 to repeat same.

[0166] Step S56:

[0167] The CPU 46 supplies a control signal to the video control section 41 to cause same to stop the encoding process.

[0168] Step S57:

[0169] The CPU 46 writes specification information, such as one shown in FIG. 8, into a predetermined region of the SDRAM 21, whereupon the process is ended.

[0170]FIG. 11 illustrates the manner of how commands are exchanged between the CPU 19 and the MPEG2 encoder 40. In the following description, reference is made to this figure.

[0171] First, the encode start command is sent from the CPU 19 to the MPEG2 encoder 40 (Step S60), whereupon the MPEG2 encoder 40 performs the encoding process.

[0172] Subsequently, if “copy not permitted” is detected as the copy protection information, the MPEG2 encoder 40 generates an interrupt with respect to the CPU 19 (Step S61).

[0173] If, as a result, the interrupt attributable to “copy not permitted” is generated the predetermined number of times, the CPU 19 supplies the encode stop command to the MPEG2 encoder 40 (Step S62). On receiving the encode stop command, the MPEG2 encoder 40 stops the encoding process.

[0174] Subsequently, the MPEG2 encoder 40 writes the specification information into a predetermined region of the SDRAM 21 (Step S63). As a consequence, the CPU 19 reads out the specification information from the SDRAM 21 and requests the IDE I/F 14 to delete the range of data specified by the specification information.

[0175] The process described above permits data already stored in the HDD 15 to be deleted afterward while at the same time specifying a range to be deleted, as mentioned above.

[0176] In the above embodiment, the encoding process is stopped when “copy not permitted” has been detected a plurality of times. In cases where the influence of noise is small, the encoding process may be stopped at the time when “copy not permitted” is detected once.

[0177] Also, in the embodiment, when “copy not permitted” has been detected a plurality of times, information specifying the part with respect to which “copy not permitted” was detected first is output, but information specifying some other part than the head may alternatively be output.

[0178] Further, in the foregoing embodiment, an interrupt is generated each time “copy not permitted” is detected, and when “copy not permitted” has been detected a predetermined number of times, the CPU 19 judges that the encoding should be stopped. The MPEG2 encoder 40 may alternatively count the number of times “copy not permitted” is detected, and when the count has reached a predetermined number, the MPEG2 encoder 40 may stop the encoding process by itself and supply the specification information to the CPU 19.

[0179] In the above embodiment, moreover, the encoding is stopped when “copy not permitted” has been detected consecutively a plurality of times. Alternatively, the encoding process may be stopped when, for example, among a plurality of times the detection is performed, “copy not permitted” is detected a predetermined number of times or more (e.g., “copy not permitted” is detected eight times or more out of ten times of detection).

[0180] The foregoing description of the embodiment is directed only to the case where “copy not permitted” is detected. Where “one copy permitted” is detected, “copy not permitted” may be recorded in place of “one copy permitted” when picture is recorded for the first time, for example, whereby copying is prohibited thereafter by the same process as described above.

[0181] Further, MPEG2 encoder is taken as a example in the above description of the embodiment, but the present invention is of course not limited to such application alone.

[0182] As described above, according to the present invention, a semiconductor device for compressing picture signal comprises input portion for receiving an input picture signal, copy protection information detecting portion for detecting copy protection information included in the picture signal input from the input portion, compressing portion for compressing the picture signal, and compressed data output portion for outputting compressed data obtained by the compressing portion, whereby illegal copying can be effectively prevented.

[0183] The foregoing is considered as illustrative only of the principles of the present invention. Further, since numerous modifications and changes will readily occur to those skilled in the art, it is not desired to limit the invention to the exact construction and applications shown and described, and accordingly, all suitable modifications and equivalents may be regarded as falling within the scope of the invention in the appended claims and their equivalents. 

What is claimed is:
 1. A semiconductor device for compressing picture signal, comprising: input portion for receiving a picture signal; copy protection information detecting portion for detecting copy protection information included in the picture signal input from the input portion; compressing portion for compressing the picture signal; and compressed data output portion for outputting compressed data obtained by the compressing portion.
 2. The semiconductor device according to claim 1, further comprising specification information output portion for outputting specification information specifying a corresponding part of the compressed data in response to detection of the copy protection information by the copy protection information detecting portion.
 3. The semiconductor device according to claim 2, wherein, when the copy protection information has been detected a plurality of times by the copy protection information detecting portion, the specification information output portion outputs information specifying at least one of a set of copy protection information detected the plurality of times.
 4. The semiconductor device according to claim 2, wherein the specification information indicates an amount of data from a head of the compressed data to the corresponding part of same, to thereby specify a position where the copy protection information has been detected.
 5. The semiconductor device according to claim 1, further comprising compressing operation stopping portion for stopping compressing operation of the compressing portion when the copy protection information has been detected a predetermined number of times by the copy protection information detecting portion. 